Neural Networks for Scalable Temporal Logic Model Verification in Hardware Verification

Ensuring the accuracy of electronic designs is essential, as hardware failures are permanent in post-production and can compromise the reliability of software or the security of cyber-physical systems. Verification is fundamental to digital circuit engineering, and FPGA and IC/ASIC projects spend 40% and 60% of their time, respectively, on this process. While testing approaches such as targeted or restricted randomized testing are easy to implement, they are inherently non-comprehensive and cannot guarantee the absence of critical errors. Formal verification, particularly model checking, addresses these limitations by mathematically confirming whether a design satisfies its specifications in all possible executions. However, methods such as BDD and SAT solvers remain computationally intensive and have difficulty adapting to complex circuits. Engineers often rely on bounded model checking to reduce computational demands, sacrificing global correctness over long time horizons.

Formal verification has evolved over decades, and temporal logic plays a key role in describing system behaviors. Based on linear temporal logic (LTL), SystemVerilog assertions are widely used to define safety and liveness properties. Security properties are efficiently verified using BDD, while SAT-based methods scale better for bounded model checking, but remain incomplete without reaching impractically high thresholds. Advanced techniques such as IC3 and Craig Interpolation enhance unbounded safety verification, while fixed-point Emerson-Lei and k-liveness calculations extend verification to liveness properties. Verifying systems with complex arithmetic remains challenging and often requires explicit state abstractions, inductive invariants, or ranking functions. Originally developed for software termination analysis, classification functions have been generalized for hardware life verification, incorporating lexicographic, nonlinear, and piecewise-defined methods to address the complexities of modern systems.

Researchers from the University of Birmingham, amazon Web Services and Queen Mary University of London have developed a machine learning-based approach to hardware model checking that integrates neural networks and symbolic reasoning. Their method uses neural networks to represent test certificates for LTL specifications, trained from randomly generated system runs. The approach ensures formal correctness over unlimited time horizons by employing satisfiability resolution to validate these certificates. Experiments demonstrate its effectiveness, outperforming academic and commercial model checkers in speed and task completion on standard hardware verification problems, contributing to improved security and reliability in system designs.

LTL model checking checks whether all possible sequences of actions in a system (M) comply with a given LTL formula (Phi), which describes the desired temporal properties. System (M) includes input and state variables, and its behavior is determined by transition rules. To check this, (Phi) is converted into a type of automaton called a Büchi automaton (A_Phi). The verification ensures that the combined system (M) and the automaton (A_neg Phi) (representing the negation of the formula) do not have valid infinite sequences. Neural classification functions help demonstrate completion and are validated using SMT solvers.

The experimental evaluation tested 194 verification tasks derived from 10 parameterized hardware designs with varying complexity. A prototype neural model checking tool was developed, using Spot to generate automata, Verilator for data generation, PyTorch for training, and Bitwuzla for SMT resolution. The tool was benchmarked against industry leaders ABC, nuXmv, and anonymous tools SMT verification. Although it is generally faster, I had problems with trivial tasks like UARTt due to overhead. Limitations of the method include reliance on word-level inputs and risks of bias in the data set.

In conclusion, the study presents an approach for temporal logic model checking using neural networks as proof certificates for hardware verification. Neural networks are trained on runs of synthetic systems, taking advantage of their ability to represent classification functions for fair termination. The method combines machine learning and symbolic reasoning by validating neural certificates with satisfiability solvers, guaranteeing formal guarantees. Applied to SystemVerilog designs, it outperforms state-of-the-art tools in scalability. Despite the computational demand of SMT resolution, the approach is effective with simple feedback networks. This marks the first successful use of neural certificates for temporal logic, laying the foundation for future advances in model checking.

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Sana Hassan, a consulting intern at Marktechpost and a dual degree student at IIT Madras, is passionate about applying technology and artificial intelligence to address real-world challenges. With a strong interest in solving practical problems, he brings a new perspective to the intersection of ai and real-life solutions.